Research paper · Research archive
Memory-Egress Cryptographic Interlock (MECI)
A Hardware-Enforced Capability-Separation Model for AI Memory Security.
Research status
Formal specification and falsifiable research program. Gated-egress safety and epoch non-resurrection are proved under stated obligations, and the finite safety projection is checked by TLC and an independent reference checker. The work reports no hardware prototype or measured performance and makes no claim of peer review.
Abstract
AI agents increasingly combine persistent memory with network, tool, file, and device capabilities. A compromised or manipulated agent can then hold readable protected state and a path through which that state can leave the trust boundary at the same time, and no instruction-level control removes that combination. This paper develops the Memory-Egress Cryptographic Interlock (MECI), a capability-separation pattern intended for hardware enforcement that makes unreleased protected information unreachable from every enabled gated egress channel. MECI formalizes high-to-egress reachability as reflexive-transitive closure over a state-dependent influence graph, gives an explicit labeling rule for sealed objects, defines a generation-checked, linearizable SafeOpen operation evaluated on the post-commit configuration, and separates gated egress from ambient observations such as timing, access patterns, and memory-bus traffic. We prove gated-egress safety from two local implementation obligations, show that a finite hazard projection refines the graph invariant under a stated soundness condition, prove epoch non-resurrection, give a counterexample showing that memory-egress mutual exclusion does not imply noninterference, and prove noninterference modulo an explicit authorized-release function in which the MECI invariant, rather than an assumed output property, carries the gated-output step. The finite safety core is specified in TLA+ and checked exhaustively within stated bounds by TLC and by an independent dependency-free reference checker. The two agree exactly on reachable-state counts for all five modeled designs, find no violation in the atomic and generation-checked designs, and return shortest counterexamples for three deliberately weakened designs. The paper also gives an Arm CCA/RMM refinement path, a GPU quiescence contract, a representative declassification policy for an AI incident-triage agent, and a comparison with CHERI, seL4, and WASI. No current confidential-computing platform is claimed to implement MECI; the work is a formal specification and falsifiable research program.
Known limitations
- Model checking is bounded (GenBound=3, MaxEpoch=3, with sensitivity runs to (5,4)) and covers the finite projection, not the full influence graph; transfer to the gated-egress invariant rests on the paper's projection-soundness assumption.
- The safety and noninterference theorems are paper proofs; there is not yet a mechanized relational proof of the noninterference theorem.
- There is no hardware prototype and no performance measurement; the performance section is a cost model.
- Ambient channels and physical attacks are outside the baseline theorem unless a deployment profile proves equivalence for them.
- Declassifier correctness is assumed. LLM-generated text stays high until a verifier or authorized reviewer releases it, which limits utility for free-form outputs.
- The influence graph is only as good as its edges; an omitted concrete dependency makes the abstraction unsound.
Summarized from the paper. The full list is in its section on limitations, failure modes, and open research problems.
Artifacts
- DOI10.5281/zenodo.23109676
- PaperPDF, version 1.0.0
- SourcePaper source and reproduction script
- ReleaseVersion 1.0.0
- ArchiveZenodo record
- AuthorORCID 0009-0001-6573-385X
Cite this work
Plain text
Thor, T. (2026). Memory-Egress Cryptographic Interlock: A Hardware-Enforced
Capability-Separation Model for AI Memory Security (1.0.0). Zenodo.
https://doi.org/10.5281/zenodo.23109676
BibTeX
@misc{thor2026meci,
author = {Thor, Thor},
title = {Memory-Egress Cryptographic Interlock: A Hardware-Enforced Capability-Separation Model for AI Memory Security},
year = {2026},
version = {1.0.0},
publisher = {Zenodo},
doi = {10.5281/zenodo.23109676},
url = {https://doi.org/10.5281/zenodo.23109676}
}
Version history
- Version 1.0.0 · Archival release on Zenodo; concepts first shared publicly on 2026-08-10.